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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/HuangYLC22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dun-An_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Harry_H._Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jing-Jia_Liou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zih-Ming_Huang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS56056.2022.00037>
foaf:homepage <https://doi.org/10.1109/ATS56056.2022.00037>
dc:identifier DBLP conf/ats/HuangYLC22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS56056.2022.00037 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label FPGA-Based Emulation for Accelerating Transient Fault Reduction Analysis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dun-An_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Harry_H._Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jing-Jia_Liou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zih-Ming_Huang>
swrc:pages 144-149 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/HuangYLC22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/HuangYLC22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2022.html#HuangYLC22>
rdfs:seeAlso <https://doi.org/10.1109/ATS56056.2022.00037>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:title FPGA-Based Emulation for Accelerating Transient Fault Reduction Analysis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document