An effective BIST design for PLA.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ats/Jou95
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1995
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An effective BIST design for PLA.
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built-in self test; programmable logic arrays; integrated circuit testing; automatic testing; combinational circuits; logic testing; CMOS logic circuits; BIST design; PLA; deterministic test pattern generator; cross point; AND array; multiple input signature register; characteristic polynomial; fault detection capability; stuck-at fault model; contact fault model
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An effective BIST design for PLA.
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