[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/KajiharaSPR00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Seiji_Kajihara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takashi_Shimono>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893616>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893616>
dc:identifier DBLP conf/ats/KajiharaSPR00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893616 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Enhanced untestable path analysis using edge graphs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Seiji_Kajihara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takashi_Shimono>
swrc:pages 139-144 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/KajiharaSPR00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/KajiharaSPR00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#KajiharaSPR00>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893616>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject logic circuits; logic testing; untestable path analysis; edge graphs; path delay fault testing; logic circuits; partial path sensitization; edge graph (xsd:string)
dc:title Enhanced untestable path analysis using edge graphs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document