Peak-power reduction for multiple-scan circuits during test application.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ats/LeeHC00
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2000
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Peak-power reduction for multiple-scan circuits during test application.
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logic testing; boundary scan testing; delays; application specific integrated circuits; integrated circuit testing; peak-power reduction; logic testing; multiple scan chain based circuits; peak periodicity; peak width; power waveforms; scan-based circuits; delay buffers; interleaving scan technique; data output; SOC
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Peak-power reduction for multiple-scan circuits during test application.
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