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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/MaedaK00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kozo_Kinoshita>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Toshiyuki_Maeda>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893648>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893648>
dc:identifier DBLP conf/ats/MaedaK00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893648 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Memory reduction of IDDQ test compaction for internal and external bridging faults. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kozo_Kinoshita>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Toshiyuki_Maeda>
swrc:pages 350-355 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/MaedaK00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/MaedaK00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#MaedaK00>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893648>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject CMOS logic circuits; sequential circuits; logic testing; integrated circuit testing; fault simulation; automatic testing; memory reduction; I/sub DDQ/ test compaction; internal bridging faults; external bridging faults; CMOS circuits; test application time reduction; IDDQ test sequence; reassignment method; sequential circuits; weighted random sequences (xsd:string)
dc:title Memory reduction of IDDQ test compaction for internal and external bridging faults. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document