Deterministic test generation for non-classical faults on the gate level.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ats/MahlstedtAH95
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1995
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Deterministic test generation for non-classical faults on the gate level.
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combinational circuits; fault diagnosis; logic testing; logic CAD; design for testability; automatic test software; CMOS logic circuits; deterministic algorithms; deterministic test pattern generator; combinational circuits; CONTEST; gate level fault models; stuck-at faults; function conversions; bridging faults; transition faults; nonclassical faults; fault simulator; fault list generator; library-based fault modeling strategy; test efficiency; ISCAS benchmark circuits; algorithm; scan-based circuits; CMOS cell library; logic simulation; ATPG
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Deterministic test generation for non-classical faults on the gate level.
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