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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/MinZL95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yinghua_Min>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhongcheng_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhuxing_Zhao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.1995.485312>
foaf:homepage <https://doi.org/10.1109/ATS.1995.485312>
dc:identifier DBLP conf/ats/MinZL95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.1995.485312 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Boolean process-an analytical approach to circuit representation (II). (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yinghua_Min>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhongcheng_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhuxing_Zhao>
swrc:pages 26-32 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/MinZL95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/MinZL95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats1995.html#MinZL95>
rdfs:seeAlso <https://doi.org/10.1109/ATS.1995.485312>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject Boolean functions; VLSI; integrated circuit design; logic design; polynomials; waveform analysis; timing; design for testability; Boolean process; logical design; VLSI circuits; performance enhancement; circuit representation; timing behavior; logical behavior; waveform functions; mathematical tools; waveform polynomials; input transitions; circuit delay (xsd:string)
dc:title Boolean process-an analytical approach to circuit representation (II). (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document