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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shahrzad_Mirkhani>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zainalabedin_Navabi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2002.1181740>
foaf:homepage <https://doi.org/10.1109/ATS.2002.1181740>
dc:identifier DBLP conf/ats/MirkhaniLN02 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2002.1181740 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Meisam_Lavasani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shahrzad_Mirkhani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zainalabedin_Navabi>
swrc:pages 374- (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/ATS.2002.1181740>
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dc:title Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document