trees (mathematics); scheduling; least mean squares methods; VLSI; integrated circuit testing; automatic test pattern generation; high level synthesis; fault diagnosis; logic testing; distribution-graph based approach; extended tree growing technique; power-constrained block-test scheduling; unequal-length block-test scheduling; power dissipation constraints; test concurrency; assigned power dissipation limits; balanced test power dissipation; least mean square error function; global priority function; system-level test scheduling algorithm
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