[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/PomeranzR00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893611>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893611>
dc:identifier DBLP conf/ats/PomeranzR00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893611 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label On the feasibility of fault simulation using partial circuit descriptions. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
swrc:pages 108-113 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/PomeranzR00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/PomeranzR00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#PomeranzR00>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893611>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject fault simulation; logic testing; fault simulation; partial circuit description; gate-level circuits; subcircuits; memory requirements (xsd:string)
dc:title On the feasibility of fault simulation using partial circuit descriptions. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document