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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/PomeranzR00a>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893643>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893643>
dc:identifier DBLP conf/ats/PomeranzR00a (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893643 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Reducing test application time for full scan circuits by the addition of transfer sequences. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
swrc:pages 317-322 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/PomeranzR00a/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/PomeranzR00a>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#PomeranzR00a>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893643>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject logic testing; boundary scan testing; fault diagnosis; automatic testing; design for testability; test application time; full scan circuits; transfer sequences; test set; primary input vectors; scan-in operation; scan-out operation; static compaction procedure; fault detection; compaction levels (xsd:string)
dc:title Reducing test application time for full scan circuits by the addition of transfer sequences. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document