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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/RavikumarSA95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._P._Ravikumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gurjeet_S._Saund>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nidhi_Agrawal>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.1995.485336>
foaf:homepage <https://doi.org/10.1109/ATS.1995.485336>
dc:identifier DBLP conf/ats/RavikumarSA95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.1995.485336 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label A STAFAN-like functional testability measure for register-level circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._P._Ravikumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gurjeet_S._Saund>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nidhi_Agrawal>
swrc:pages 192-198 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/1995>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats1995.html#RavikumarSA95>
rdfs:seeAlso <https://doi.org/10.1109/ATS.1995.485336>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject shift registers; design for testability; circuit analysis computing; fault diagnosis; logic testing; statistical analysis; reliability theory; performance evaluation; functional testability measure; register-level circuits; fault coverage; digital circuit; stuck-at fault model; fault simulation; testability analysis programs; SCOAP; gate-level digital circuits; logic gates; high-level synthesis; testability-driven synthesis; adders; multipliers; multiplexers; busses; F-STAFAN; Sun/SPARC workstation (xsd:string)
dc:title A STAFAN-like functional testability measure for register-level circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document