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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/RenovellHB95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michel_Renovell>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/P._Huc>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yves_Bertrand>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.1995.485323>
foaf:homepage <https://doi.org/10.1109/ATS.1995.485323>
dc:identifier DBLP conf/ats/RenovellHB95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.1995.485323 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Serial transistor network modeling for bridging fault simulation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michel_Renovell>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/P._Huc>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yves_Bertrand>
swrc:pages 100-106 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/RenovellHB95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/RenovellHB95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats1995.html#RenovellHB95>
rdfs:seeAlso <https://doi.org/10.1109/ATS.1995.485323>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject CMOS logic circuits; fault diagnosis; logic testing; SPICE; integrated circuit modelling; integrated circuit testing; digital simulation; circuit analysis computing; serial transistor network modeling; bridging fault simulation; voting model; biased voting model; relative transistor strength; SPICE pre-simulation; fault simulation procedure; CMOS logic (xsd:string)
dc:title Serial transistor network modeling for bridging fault simulation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document