[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/Savir95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jacob_Savir>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.1995.485339>
foaf:homepage <https://doi.org/10.1109/ATS.1995.485339>
dc:identifier DBLP conf/ats/Savir95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.1995.485339 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Generator choices for delay test. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jacob_Savir>
swrc:pages 214-221 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/Savir95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/Savir95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats1995.html#Savir95>
rdfs:seeAlso <https://doi.org/10.1109/ATS.1995.485339>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject built-in self test; boundary scan testing; fault diagnosis; logic testing; delays; shift registers; automatic testing; VLSI; integrated circuit testing; BIST based delay test; generator choices; test vectors; timing requirement; delay test vector generator; scan designs; nonscan designs; performance; cost; flexibility; linear feedback shift register; transition test; skewed-load delay test; pseudo-random test; shift dependency; digital logic circuits; ATPG (xsd:string)
dc:title Generator choices for delay test. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document