Functional test generation for path delay faults.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ats/SrinivasAB95
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1995
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Functional test generation for path delay faults.
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programmable logic arrays; delays; multivalued logic; fault location; fault diagnosis; logic testing; functional test generation; path delay faults; programmable logic arrays; PLA; growth faults; disappearance faults; robustly detectable path delay faults; two-level circuit; algebraic transformations; generated vectors; stuck faults; algebraically factored multilevel circuit; timings; fault coverages; scan/hold versions; ISCAS89 circuits
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Functional test generation for path delay faults.
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