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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/SuHJT96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chauchin_Su>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shyh-Jye_Jou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shyh-Shen_Hwang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuan-Tzu_Ting>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.1996.555138>
foaf:homepage <https://doi.org/10.1109/ATS.1996.555138>
dc:identifier DBLP conf/ats/SuHJT96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.1996.555138 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Syndrome Simulation And Syndrome Test For Unscanned Interconnects. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chauchin_Su>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shyh-Jye_Jou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shyh-Shen_Hwang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuan-Tzu_Ting>
swrc:pages 62-67 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/SuHJT96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/SuHJT96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats1996.html#SuHJT96>
rdfs:seeAlso <https://doi.org/10.1109/ATS.1996.555138>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject boundary scan testing; unscanned interconnects; syndrome test methodology; event driven syndrome simulation; boundary scan environment; test length; faulty syndromes; fault-free syndromes; simulation algorithm; test cost reduction; set covering problem; tolerable error rate; partially scanned PCB; MCM; test pattern generation; weighted random patterns; board level testing (xsd:string)
dc:title Syndrome Simulation And Syndrome Test For Unscanned Interconnects. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document