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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/Sur-KolayRSCR00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ken_S._Stevens>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marly_Roncken>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Parimal_Pal_Chaudhuri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rob_Roy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Susmita_Sur-Kolay>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893612>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893612>
dc:identifier DBLP conf/ats/Sur-KolayRSCR00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893612 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Fsimac: a fault simulator for asynchronous sequential circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ken_S._Stevens>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marly_Roncken>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Parimal_Pal_Chaudhuri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rob_Roy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Susmita_Sur-Kolay>
swrc:pages 114-119 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/Sur-KolayRSCR00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/Sur-KolayRSCR00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#Sur-KolayRSCR00>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893612>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject asynchronous circuits; sequential circuits; timing; fault simulation; logic testing; cellular automata; built-in self test; iterative methods; asynchronous sequential circuits; fault simulator; Fsimac; gate-level fault simulator; stuck-at faults; gate-delay faults; combinational logic; Muller C-elements; complex domino gates; high-speed design; feedback loops; iterations; min-max timing analysis; delay faults; min-max rime stamps; pseudo-random tests; Cellular Automata; CA-BIST; waveform model (xsd:string)
dc:title Fsimac: a fault simulator for asynchronous sequential circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document