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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/TakahashiBTM97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Takahashi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kwame_Osei_Boateng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Toshiyuki_Matsunaga>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuzo_Takamatsu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.1997.643977>
foaf:homepage <https://doi.org/10.1109/ATS.1997.643977>
dc:identifier DBLP conf/ats/TakahashiBTM97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.1997.643977 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Takahashi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kwame_Osei_Boateng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Toshiyuki_Matsunaga>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuzo_Takamatsu>
swrc:pages 320-325 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/TakahashiBTM97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/TakahashiBTM97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats1997.html#TakahashiBTM97>
rdfs:seeAlso <https://doi.org/10.1109/ATS.1997.643977>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject test generation, gate delay faults, marginal delay, combinational circuit (xsd:string)
dc:title A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document