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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/UedaK95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroaki_Ueda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kozo_Kinoshita>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.1995.485361>
foaf:homepage <https://doi.org/10.1109/ATS.1995.485361>
dc:identifier DBLP conf/ats/UedaK95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.1995.485361 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Low power design and its testability. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroaki_Ueda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kozo_Kinoshita>
swrc:pages 361-366 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/UedaK95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/UedaK95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats1995.html#UedaK95>
rdfs:seeAlso <https://doi.org/10.1109/ATS.1995.485361>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject CMOS logic circuits; probability; design for testability; delays; fault location; fault diagnosis; logic testing; automatic test software; logic CAD; low power design; power reduction tool; PORT; power dissipation factor; transition probability; testability; redundant faults; testability parameters; stuck-at faults; delay faults; CMOS circuit (xsd:string)
dc:title Low power design and its testability. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document