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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/WuT00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chuan_Yi_Tang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wen-Jer_Wu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893639>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893639>
dc:identifier DBLP conf/ats/WuT00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893639 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Memory test time reduction by interconnecting test items. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chuan_Yi_Tang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wen-Jer_Wu>
swrc:pages 290-298 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/WuT00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/WuT00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#WuT00>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893639>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject integrated memory circuits; integrated circuit testing; linear programming; integer programming; graph theory; memory test time reduction; test items interconnection; initialization sequences; verification sequences; signal settling time; interconnection problem; rural Chinese postman problem; NP-hard problem; integer linear programming model; successive ILP models; constraints; iterations (xsd:string)
dc:title Memory test time reduction by interconnecting test items. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document