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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ats/XuC00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shiyi_Xu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Cen>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FATS.2000.893622>
foaf:homepage <https://doi.org/10.1109/ATS.2000.893622>
dc:identifier DBLP conf/ats/XuC00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FATS.2000.893622 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Forecasting the efficiency of test generation algorithms for digital circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shiyi_Xu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Cen>
swrc:pages 179- (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ats/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ats/XuC00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ats/XuC00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ats/ats2000.html#XuC00>
rdfs:seeAlso <https://doi.org/10.1109/ATS.2000.893622>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject integrated circuit testing; VLSI; genetic algorithms; digital integrated circuits; sequential circuits; combinational circuits; logic testing; automatic test pattern generation; test generation algorithms; efficiency forecasting; digital circuits; VLSI circuits; testability parameters; combinational circuits; sequential circuits; genetic algorithms; ATPG (xsd:string)
dc:title Forecasting the efficiency of test generation algorithms for digital circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document