Unified scan design with scannable memory arrays. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

Property	Value
dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/ats/Yano95>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Seiken_Yano>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FATS.1995.485331>
foaf:homepage	<https://doi.org/10.1109/ATS.1995.485331>
dc:identifier	DBLP conf/ats/Yano95 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FATS.1995.485331 (xsd:string)
dcterms:issued	1995 (xsd:gYear)
rdfs:label	Unified scan design with scannable memory arrays. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Seiken_Yano>
swrc:pages	153-159 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/ats/1995>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/ats/Yano95/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/ats/Yano95>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/ats/ats1995.html#Yano95>
rdfs:seeAlso	<https://doi.org/10.1109/ATS.1995.485331>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/ats>
dc:subject	design for testability; logic CAD; integrated memory circuits; automatic testing; fault diagnosis; flip-flops; arrays; shift registers; unified scan design; scannable memory arrays; design-for-testability; flip-flops; single scan path; scan operation time; scannable register file (xsd:string)
dc:title	Unified scan design with scannable memory arrays. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:InProceedings
rdf:type	foaf:Document