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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/baip/KannanAAND10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._J._Daniel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Krishnan_Nived>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/M._Arunkumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Megalingam_Rajesh_Kannan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/V._Arjun_Ashok>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-642-12214-9%5F19>
foaf:homepage <https://doi.org/10.1007/978-3-642-12214-9_19>
dc:identifier DBLP conf/baip/KannanAAND10 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-642-12214-9%5F19 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Power-Efficient Cache Design Using Dual-Edge Clocking Scheme in Sun OpenSPARC T1 and Alpha AXP Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._J._Daniel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Krishnan_Nived>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/M._Arunkumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Megalingam_Rajesh_Kannan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/V._Arjun_Ashok>
swrc:pages 108-113 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/baip/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/baip/KannanAAND10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/baip/KannanAAND10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/baip/baip2010.html#KannanAAND10>
rdfs:seeAlso <https://doi.org/10.1007/978-3-642-12214-9_19>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/baip>
dc:title Power-Efficient Cache Design Using Dual-Edge Clocking Scheme in Sun OpenSPARC T1 and Alpha AXP Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document