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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/bmas/PriyadarshiKSH10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_B._Steer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nikhil_Kriplani>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shivam_Priyadarshi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/T._Robert_Harris>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FBMAS.2010.6156602>
foaf:homepage <https://doi.org/10.1109/BMAS.2010.6156602>
dc:identifier DBLP conf/bmas/PriyadarshiKSH10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FBMAS.2010.6156602 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Fast dynamic simulation of VLSI circuits using reduced order compact macromodel of standard cells. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_B._Steer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nikhil_Kriplani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shivam_Priyadarshi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/T._Robert_Harris>
swrc:pages 75-80 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/bmas/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/bmas/PriyadarshiKSH10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/bmas/PriyadarshiKSH10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/bmas/bmas2010.html#PriyadarshiKSH10>
rdfs:seeAlso <https://doi.org/10.1109/BMAS.2010.6156602>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/bmas>
dc:title Fast dynamic simulation of VLSI circuits using reduced order compact macromodel of standard cells. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document