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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/camp/ZingirianM00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Massimo_Maresca>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nicola_Zingirian>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FCAMP.2000.875985>
foaf:homepage <https://doi.org/10.1109/CAMP.2000.875985>
dc:identifier DBLP conf/camp/ZingirianM00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FCAMP.2000.875985 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Massimo_Maresca>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nicola_Zingirian>
swrc:pages 261-269 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/camp/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/camp/ZingirianM00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/camp/ZingirianM00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/camp/camp2000.html#ZingirianM00>
rdfs:seeAlso <https://doi.org/10.1109/CAMP.2000.875985>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/camp>
dc:subject embedded systems; loop regularization; video processing; image processing; instruction level parallel architectures; instruction reordering; register renaming; embedded systems; digital signal processors (xsd:string)
dc:title Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document