A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/cases/SasanHEK09
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2009
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A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).
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fault tolerance, low power cache, low power design, low power memory organization, memory organization., remapping cache, variation aware cache, vfs
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A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).
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