A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/cata/HakhamaneshiA10
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/cata/HakhamaneshiA10
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Bahram_Hakhamaneshi
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Behnam_S._Arad
>
dc:
identifier
DBLP conf/cata/HakhamaneshiA10
(xsd:string)
dcterms:
issued
2010
(xsd:gYear)
rdfs:
label
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Bahram_Hakhamaneshi
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Behnam_S._Arad
>
swrc:
pages
224-227
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/cata/2010
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/cata/HakhamaneshiA10/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/cata/HakhamaneshiA10
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/cata/cata2010.html#HakhamaneshiA10
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/cata
>
dc:
title
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document