[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/cav/VijayaraghavanC15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Adam_Chlipala>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arvind>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Muralidaran_Vijayaraghavan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nirav_Dave>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-319-21668-3%5F7>
foaf:homepage <https://doi.org/10.1007/978-3-319-21668-3_7>
dc:identifier DBLP conf/cav/VijayaraghavanC15 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-319-21668-3%5F7 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label Modular Deductive Verification of Multiprocessor Hardware Designs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Adam_Chlipala>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arvind>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Muralidaran_Vijayaraghavan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nirav_Dave>
swrc:pages 109-127 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/cav/2015>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/cav/VijayaraghavanC15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/cav/VijayaraghavanC15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/cav/cav2015.html#VijayaraghavanC15>
rdfs:seeAlso <https://doi.org/10.1007/978-3-319-21668-3_7>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/cav>
dc:title Modular Deductive Verification of Multiprocessor Hardware Designs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document