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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Doosan_Cho>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gang-Ryung_Uh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ravi_Ayyagari>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yunheung_Paek>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-71229-9%5F2>
foaf:homepage <https://doi.org/10.1007/978-3-540-71229-9_2>
dc:identifier DBLP conf/cc/ChoAUP07 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-71229-9%5F2 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Doosan_Cho>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gang-Ryung_Uh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ravi_Ayyagari>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yunheung_Paek>
swrc:pages 16-31 (xsd:string)
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owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/cc/ChoAUP07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/cc/ChoAUP07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/cc/cc2007.html#ChoAUP07>
rdfs:seeAlso <https://doi.org/10.1007/978-3-540-71229-9_2>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/cc>
dc:title Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document