Estimating Post-Synthesis Area, Delay, and Leakage Power of Standard Cell Based FPGA Tiles. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FCCECE58730.2023.10289025>
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dc:title	Estimating Post-Synthesis Area, Delay, and Leakage Power of Standard Cell Based FPGA Tiles. (xsd:string)
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