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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ccece/WangCLJK09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bangli_Liang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bo_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dianyong_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinguang_Jiang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tad_A._Kwasniewski>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FCCECE.2009.5090320>
foaf:homepage <https://doi.org/10.1109/CCECE.2009.5090320>
dc:identifier DBLP conf/ccece/WangCLJK09 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FCCECE.2009.5090320 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bangli_Liang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bo_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dianyong_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinguang_Jiang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tad_A._Kwasniewski>
swrc:pages 1221-1226 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ccece/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ccece/WangCLJK09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ccece/WangCLJK09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ccece/ccece2009.html#WangCLJK09>
rdfs:seeAlso <https://doi.org/10.1109/CCECE.2009.5090320>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ccece>
dc:title A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document