Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ccs/ToriiYM16
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Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs.
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Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs.
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