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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/cdes/Alghazo06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jaafar_Alghazo>
dc:identifier DBLP conf/cdes/Alghazo06 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jaafar_Alghazo>
swrc:pages 39-45 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/cdes/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/cdes/Alghazo06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/cdes/Alghazo06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/cdes/cdes2006.html#Alghazo06>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/cdes>
dc:title Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document