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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/cdes/AlghazoB05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jaafar_Alghazo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nazeih_Botros>
dc:identifier DBLP conf/cdes/AlghazoB05 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jaafar_Alghazo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nazeih_Botros>
swrc:pages 136-142 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/cdes/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/cdes/AlghazoB05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/cdes/AlghazoB05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/cdes/cdes2005.html#AlghazoB05>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/cdes>
dc:title Modeling and Synthesis of a Modified Floating Point Fused Multiply-Add (FMA) Arithmetic Unit Using VHDL and FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document