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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/cdes/SharmaSCRKC08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nitin_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rohit_Sharma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Saumya_Rawat>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sonia_Chadha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vinodini_Kapoor>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vivek_Kumar_Sehgal>
dc:identifier DBLP conf/cdes/SharmaSCRKC08 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Time-Domain Analysis of VLSI Interconnects Considering Oscillatory Inputs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nitin_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rohit_Sharma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Saumya_Rawat>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sonia_Chadha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vinodini_Kapoor>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vivek_Kumar_Sehgal>
swrc:pages 57-60 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/cdes/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/cdes/SharmaSCRKC08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/cdes/SharmaSCRKC08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/cdes/cdes2008.html#SharmaSCRKC08>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/cdes>
dc:title Time-Domain Analysis of VLSI Interconnects Considering Oscillatory Inputs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document