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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/cescit/GarciaGSCCET12>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Adriano_Tavares>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Filipe_Salgado>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jorge_Cabral_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mongkol_Ekpanyapong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paulo_Cardoso>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paulo_Garcia>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tiago_Gomes>
foaf:homepage <http://dx.doi.org/doi.org%2F10.3182%2F20120403-3-DE-3010.00005>
foaf:homepage <https://doi.org/10.3182/20120403-3-DE-3010.00005>
dc:identifier DBLP conf/cescit/GarciaGSCCET12 (xsd:string)
dc:identifier DOI doi.org%2F10.3182%2F20120403-3-DE-3010.00005 (xsd:string)
dcterms:issued 2012 (xsd:gYear)
rdfs:label A Fault Tolerant Design Methodology for a FPGA-Based Softcore Processor. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Adriano_Tavares>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Filipe_Salgado>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jorge_Cabral_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mongkol_Ekpanyapong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paulo_Cardoso>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paulo_Garcia>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tiago_Gomes>
swrc:pages 145-150 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.3182/20120403-3-DE-3010.00005>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/cescit>
dc:title A Fault Tolerant Design Methodology for a FPGA-Based Softcore Processor. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document