Performance/area efficiency in chip multiprocessors with micro-caches.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/cf/BecchiFC07
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2007
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Performance/area efficiency in chip multiprocessors with micro-caches.
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cache hierarchies, chip multiprocessor, networking workload
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Performance/area efficiency in chip multiprocessors with micro-caches.
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