Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/cf/HomayounSGVKD10
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Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
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leakage power, multiple sleep mode, peripheral circuits, sram memory, temperature reduction.
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Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.
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