An efficient wakeup design for energy reduction in high-performance superscalar processors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/cf/HsiaoC05
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2005
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An efficient wakeup design for energy reduction in high-performance superscalar processors.
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high performance, issue window, low power, wakeup logic
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An efficient wakeup design for energy reduction in high-performance superscalar processors.
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