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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ches/GoodB05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mohammed_Benaissa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tim_Good>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F11545262%5F31>
foaf:homepage <https://doi.org/10.1007/11545262_31>
dc:identifier DBLP conf/ches/GoodB05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F11545262%5F31 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label AES on FPGA from the Fastest to the Smallest. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mohammed_Benaissa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tim_Good>
swrc:pages 427-440 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ches/2005>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ches/GoodB05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ches/GoodB05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ches/ches2005.html#GoodB05>
rdfs:seeAlso <https://doi.org/10.1007/11545262_31>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ches>
dc:subject Advanced Encryption Standard (AES), Field Programmable Gate Array (FPGA), finite field, design exploration, high throughput, pipelined, low area, Application Specific Instruction Processor (ASIP). (xsd:string)
dc:title AES on FPGA from the Fastest to the Smallest. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document