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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ches/HomsirikamolRG11>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ekawat_Homsirikamol>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kris_Gaj>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marcin_Rogawski>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-642-23951-9%5F32>
foaf:homepage <https://doi.org/10.1007/978-3-642-23951-9_32>
dc:identifier DBLP conf/ches/HomsirikamolRG11 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-642-23951-9%5F32 (xsd:string)
dcterms:issued 2011 (xsd:gYear)
rdfs:label Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ekawat_Homsirikamol>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kris_Gaj>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marcin_Rogawski>
swrc:pages 491-506 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ches/2011>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ches/HomsirikamolRG11/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ches/HomsirikamolRG11>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ches/ches2011.html#HomsirikamolRG11>
rdfs:seeAlso <https://doi.org/10.1007/978-3-642-23951-9_32>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ches>
dc:title Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document