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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bart_Preneel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois-Xavier_Standaert>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Siddika_Berna_%E2%88%9A%C4%96rs>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-28632-5%5F3>
foaf:homepage <https://doi.org/10.1007/978-3-540-28632-5_3>
dc:identifier DBLP conf/ches/StandaertOP04 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-28632-5%5F3 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? (xsd:string)
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Siddika_Berna_%E2%88%9A%C4%96rs>
swrc:pages 30-44 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1007/978-3-540-28632-5_3>
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dc:title Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document