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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/ches/TillichG06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Johann_Gro%E2%88%9A%C3%BCsch%E2%88%9A%C2%A7dl>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stefan_Tillich>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F11894063%5F22>
foaf:homepage <https://doi.org/10.1007/11894063_22>
dc:identifier DBLP conf/ches/TillichG06 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F11894063%5F22 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Johann_Gro%E2%88%9A%C3%BCsch%E2%88%9A%C2%A7dl>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stefan_Tillich>
swrc:pages 270-284 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/ches/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/ches/TillichG06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/ches/TillichG06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/ches/ches2006.html#TillichG06>
rdfs:seeAlso <https://doi.org/10.1007/11894063_22>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/ches>
dc:subject Advanced Encryption Standard, instruction set extensions, embedded RISC processor, SPARC V8 architecture, efficient implementation. (xsd:string)
dc:title Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document