Low power ARM¬ģ Cortex‚ĄĘ-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/cicc/AgrawalKKKLBZRRWCRHEMTYMW13
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