Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning.
Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning.
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Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning.
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