The iFlow design factory infrastructure for a 17M-gate, 0.13őľm, 333MHz design [SoC design].
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/cicc/DescampsB03
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The iFlow design factory infrastructure for a 17M-gate, 0.13őľm, 333MHz design [SoC design].
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The iFlow design factory infrastructure for a 17M-gate, 0.13őľm, 333MHz design [SoC design].
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