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dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_E._Duarte>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Greg_Taylor>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Keng_L._Wong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mingwei_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Suching_Hsu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FCICC.2010.5617473>
foaf:homepage <https://doi.org/10.1109/CICC.2010.5617473>
dc:identifier DBLP conf/cicc/DuarteHWHT10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FCICC.2010.5617473 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_E._Duarte>
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Keng_L._Wong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mingwei_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Suching_Hsu>
swrc:pages 1-4 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/CICC.2010.5617473>
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dc:title Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document