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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/cicc/HuangMAH12>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Min_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Moty_Mehalel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ramesh_Arvapalli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Songnian_He>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FCICC.2012.6330624>
foaf:homepage <https://doi.org/10.1109/CICC.2012.6330624>
dc:identifier DBLP conf/cicc/HuangMAH12 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FCICC.2012.6330624 (xsd:string)
dcterms:issued 2012 (xsd:gYear)
rdfs:label An energy efficient 32nm 20 MB L3 cache for Intel¬ģ Xeon¬ģ processor E5 family. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Min_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Moty_Mehalel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ramesh_Arvapalli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Songnian_He>
swrc:pages 1-4 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/cicc/2012>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/cicc/HuangMAH12/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/cicc/HuangMAH12>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/cicc/cicc2012.html#HuangMAH12>
rdfs:seeAlso <https://doi.org/10.1109/CICC.2012.6330624>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/cicc>
dc:title An energy efficient 32nm 20 MB L3 cache for Intel¬ģ Xeon¬ģ processor E5 family. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document