A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Chester_Liu>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jacob_Botimer>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Zhengya_Zhang>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FCICC51472.2021.9431555>
foaf:homepage	<https://doi.org/10.1109/CICC51472.2021.9431555>
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dc:identifier	DOI doi.org%2F10.1109%2FCICC51472.2021.9431555 (xsd:string)
dcterms:issued	2021 (xsd:gYear)
rdfs:label	A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. (xsd:string)
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jacob_Botimer>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Zhengya_Zhang>
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dc:title	A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. (xsd:string)
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