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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qi_S._Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Soner_Yaldiz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Syed_Feruz_Syed_Farooq>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FCICC.2015.7338432>
foaf:homepage <https://doi.org/10.1109/CICC.2015.7338432>
dc:identifier DBLP conf/cicc/LotfyFWYMK15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FCICC.2015.7338432 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. (xsd:string)
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foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Syed_Feruz_Syed_Farooq>
swrc:pages 1-4 (xsd:string)
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dc:title A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. (xsd:string)
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rdf:type swrc:InProceedings
rdf:type foaf:Document